The present invention relates to a memory cell and particularly to a non-refresh 4T (Four-Transistor) memory cell.
To meet customer demand for smaller and more powerful, efficient integrated circuits (ICs), manufacturers are designing newer ICs that operate with lower supply voltages and include smaller internal sub-circuits such as memory cells. Many ICs, such as memory circuits or other circuits such as microprocessors having onboard memory, include one or more SRAM cells for data storage. SRAM cells are popular because they operate at a higher speed than dynamic-random-access-memory (DRAM) cells. Further as long as SRAM cells are powered, they can store data indefinitely, unlike DRAM cells, which must be periodically refreshed.
FIG. 1 is a circuit diagram of a conventional 6-transistor (6-T) SRAM cell 110, which can operate at a relatively low supply voltage, for example 2.2V-3.3V, but which is relatively large in size. A pair of NMOS access transistors 112 and 114 allow complementary bit values D and {overscore (D)} on digit lines 116 and 118, respectively, to be read from and to be written to a storage circuit 120 of the cell 110. The storage circuit 120 includes NMOS pull-down transistors 122 and 126, which are coupled in a positive-feedback configuration with PMOS pull-up transistors 124 and 128. Nodes A and B are the complementary inputs/outputs of the storage circuit 120, and the respective complementary logic values at these nodes represent the state of the cell 110. For example, when the node A is at logic 1 and the node B is at logic 0, logic 1 is stored in the cell 110. Conversely, when the node A is at logic 0 and the node B is at logic 1, then the cell 110 stores logic 0. Thus, the cell 110 is bi-stable, i.e., it can have one of two stable states, logic 1, or logic 0.
In operation during a read of the cell 110, a word-line WL, which is coupled to the gates of the transistors 112 and 114, is driven to a voltage approximately equal to Vcc to activate the transistors 112 and 114. For example, assume that Vcc=logic 1=5V and Vss=logic o=0V, and that at the beginning of the read, a logic 0 is stored in the cell 110, such that the voltage level at the node A is 0V and the voltage level at the node B is 5V. Also, assume that before the read cycle, the digit lines 116 and 118 are equilibrated at approximately Vcc. Therefore, the NMOS transistor 112 couples the node A to the digit line 116, and the NMOS transistor 114 couples the node B to the digit line 118. For example, assuming that the threshold voltages of the transistors 112 and 114 are both 1V, then the transistor 114 couples a maximum of 4V from the digit line 118 to the node B. The transistor 112, however, couples the digit line 116 to the node A, which pulls down the voltage on the digit line 116 enough (for example, 100-500 millivolts) to cause a sense amp (not shown) coupled to the lines 16 and 18 to read the cell 110 as storing a logic 0.
During a write operation, for example, of logic 1 to the cell 110, and making the same assumptions as discussed above for the read, the transistors 112 and 114 are activated as discussed above, and logic 1 is driven onto the digit line 116 and logic 0 is driven onto the digit line 118. Thus, the transistor 112 couples 4V (the 5V on the digit line 116 minus the 1V threshold of the transistor 112) to the node A, and the transistor 114 couples 0V from the digit line 118 to the node B. The low voltage on the node B turns off the NMOS transistor 126, and turns on the PMOS transistor 128. Thus, the inactive NMOS transistor 126 allows the PMOS transistor 128 to pull the node A up to 5V. This high voltage on the node A turns on the NMOS transistor 122 and turns off the PMOS transistor 124, thus allowing the NMOS transistor 122 to reinforce the logic 0 on the node B. Likewise, if the voltage written to the node B is 4V and that written to the node A is 0V, the positive-feedback configuration ensures that the cell 110 will store logic 0.
Because the PMOS transistors 126 and 128 have low on resistances (typically on the order of a few kilohms), they can often pull the respective nodes A and B virtually all the way up to Vcc in less than 10 nanoseconds (ns), and thus render the cell 110 relatively stable and allow the cell 110 to operate at a low supply voltage as discussed above. But unfortunately, the transistors 126 and 128 cause the cell 110 to be approximately 30%-40% larger than a 4-transistor (4-T) SRAM cell, which is discussed next.
FIG. 2 is a circuit diagram of a conventional 4-T SRAM cell. The cell has a cross coupled inverter. Each inverter includes a pull-down transistor T1 or T2 and a load p1 or p2, and a pair of transfer transistors T3, T4. The gate electrode of T1 is connected to the drain of T2 and the gate electrode of T2 is connected to the drain of T1 to provide a flip-flop operation. The load device p1, p2 may be depletion or enhancement transistor or a high value resistor. The load devices p1 and p2 are connected to the power supply Vdd on one side and to the drain of drive transistors T1, T2 respectively. The purpose of the resistor load p1, p2 and the power supply Vdd is to counteract the effect of charge leakage at the drains of the drive and transfer transistors (nodes N1 and N2). The gates of the transfer transistors T3, T4 are connected to a WORD line 28 and are switched ON by asserting the WORD line 28. The drain/source contacts of the transfer transistors are connected between the nodes N1, N2, and BIT lines 25, 26 respectively.
The operation of a SRAM is well known. In brief, the charge (voltage) in nodes N1 and N2 represent the logic state of the cell. For example, to write a data of “1” in node N1, the bit line 25 is pre-charged to a desired voltage and the word line 28 is asserted. Node N1 is charged up and drives N2 to a “no charge” or a low state. To read the cell, bit lines 25 and 26 are pre-charged and word line 28 is asserted. The bit line 26 is discharged through transistors T4 and T2 and the transient charge is sensed by sense amplifier-external to the cell.
A four transistor (4T) SRAM uses a high value resistor a its load device. The 4T SRAM is attractive as it has the potential for reduced cell size compared to a 6T SRAM wherein the load devices are transistors. The primary function of the load resistor is to supply enough current to compensate for the junction leakage and maintain the charge in the node. Junction leakage currents typically range from femto-ampere to pico-ampere (10−15 to 10−12 A) for FETs fabricated under contamination free conditions, which is the minimum current required from the loaded (p1, p2) power supply Vdd. The maximum resistor value acceptable is in the range of 102 to 1015 ohms, assuming a Vdd of 3 to 5 volts. The value of the resistor, in turn is affected by the availability of material that has a very high intrinsic resistance and the cell area available for resistor layout. In addition, the resistor material and process should be compatible with silicon manufacturing.
However, for on-chip storage in microprocessors and other logic circuits, the 4T-SRAMs have not been used. This is due to a complex process necessary to form a load element and thus, the 4T-SRAMs have poor stability at low voltage. In the quarter-micrometer generation and later, only 6T-SRAM cells have been reported as being used for advanced technologies to reduce the cell size, such as borderless contact, self-aligned contact, and local-interconnect.
A loadless 4T-SRAM cell is proposed by Kenji Noda et al., in the article entitled “A Loadless CMOS Four-Transistor SRAM Cell in a 0.18-μm Logic Technology” in IEEE Transactions on Electron Devices, Vol. 48, No. 12, December 2001, pp. 2851-2855. FIG. 3 shows an example of a circuit of the loadless 4T-SRAM cell. The single cell comprises two nMOSFETs 311 and 312 for drive transistors and two pMOSFETs 321 and 322 for transfer transistors. Compared with the conventional 4T-SRAM having nMOSFETs and load elements, an advantage of using pMOSFETs is that the high-node level rises immediately after a read or write operation. During a stand-by cycle, bit lines are pre-charged at the Vdd. At this point, the pMOS transfer transistors 321 and 322, which are turned off, work as load elements. In order to retain the data without a refresh cycle, an off-state current of the pMOSPET- has to be higher than that of the nMOSFET-, even when the source-drain bias for the nMOSFET is approximately 1.8 V and that for the pMOSFET is less than 0.1 V. The pMOSFET is the same as a nominal transistor in logic circuits, but the nMOSFET is given 0.25 V higher threshold voltages. The off-state current for nMOSFET at V in the saturated region is lower than that for the pMOSFET at V in a linear region by two orders of magnitude. For these MOSFETs, junction leakage current and band-to-band tunneling current are negligible when the gate bias is 0V. With sufficient margin for the difference between the nMOSFET and the pMOSFET, the high-node level cannot be retained with either a load element or a specialized circuit, at least for a single cell. In read/write operations, cell nodes have full swing signals. The maximum bit-line swings in the read cycles are approximately 1.1 V, which is sufficient for high-speed and stable read operation. When reading the cell data, the pMOS transfer gate connected to the low-node operates as a source-follower circuit.
Accordingly, the previous loadless 4T-SRAM cells are deficient in that a data signal cannot be stably sustained in cell capacitor due to several leakage paths, such as gate oxide direct tunneling, channel leakage, and junction leakage so that frequent data refreshing is necessary when the cell signals go beyond the sensing margin.